The commoditization of high performance computing to a broader range of applications coupled with the reduction in performance improvement from traditional scaling technologies has led to a broad interest in a number of new compute acceleration technologies from GPGPUs to CGRAs and FPGAs. Meanwhile, SIMD widths have been widening to try to keep up with computational demand and general purpose architectures have started incorporating features from the vector architectures that used to dominate high performance computing. From IBM's Vector Media eXtension (VMX) to NEC's SX architecture to Intel's Advanced Vector eXtension (AVX) to ARM's recently announced Scalable Vector Extension (SVE) -- all of the major general purpose architectures seem to have embraced a return to vector based functionality.

Supporting these hardware developments there are a number of features being proposed for incorporation into modern programming models and languages in order to support the vector additions as well as restructuring memory access in order to feed the computational pipelines. Meanwhile application developers have been hard at work trying to refactor code to take advantage of wider vector units and more complicated memory hierarchies. Tools and techniques for developing for these new vector architectures are still evolving, particularly on emerging languages and runtimes.

• 09:30 – 10:30 Applications
• Shivanshu Kumar Singh - “Optimizations of COAWST for a large simulation on the Earth Simulator”
• Nils Meyer - “SVE-enabling Lattice QCD Codes”
• 10:30 – 11:00 Break
• 11:00 – 12:30 Architectures and Compilers
• Angela Pohl - “Cost Modelling for Vectorization on ARM”
• Miguel Tairum Cruz - “Performing SVE studies using the Arm Instruction Emulator”
• Theodore Omtzigt - “Stillwater Knowledge Processing Unit”
• 12:30 – 13:30 Lunch

The REV-A 2018 workshop will be a full-day meeting to be held at the IEEE Cluster 2018, in Belfast, Ireland, focusing on all aspects of vector architectures, programming models, programming frameworks, and applications. Topics of interest, of both theoretical and practical significance, include but are not limited to the following topics:

• Programming framework
• Programming model and language explorations
• Compilation and optimization including:
• • algorithmic improvements
  • code optimization
• Performance Analysis and Debugging Tools
• Performance Metrics and Evaluations
• Libraries and run-time systems
• Design, generation, verification and validation of representative applications
• Case-studies of representative applications
• Innovative applications for vector architectures
• Hardware studies and micro-architectural implementation tradeoffs

The REV-A workshop proceedings will be published along with the IEEE Cluster Digital Library. Submitted manuscripts should follow the IEEE Xplore format for publication: not exceed 10 single-spaced double-column pages using 10-point size font on 8.5x11 inch pages, including figures, tables, and references. Manuscripts must be submitted electronically in PDF format. Submissions will be judged on correctness, originality, technical strength, significance, quality of presentation, and interest and relevance to the workshop attendees. Submitted papers may not have appeared in or be under consideration for another workshop, conference, or journal. Accepted papers will have a page limit of 8 pages, and authors can purchase an additional 2 pages, for a total of 10 pages maximum.

Deadlines are Anywhere on Earth (AoE)

Full Papers due:	June 25, 2018  July 2, 2018 Extended!
Paper Acceptance Notification:	July 17, 2018
Camera-ready deadline:	TBD
REV-A Workshop:	September 10, 2018

Luiz DeRose	Cray Inc.
Eric Van Hensbergen	Arm Research

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Giri Chukkapalli	Cavium
Elmootazbellah Elnozahy	KAUST
Ali Jannesari	Iowa State University
Ian Karlin	Lawrence Livermore National Laboratory
Sanyam Mehta	Cray Inc.
Jose Moreira	IBM
Hiroshi Nakashima	Kyoto University
Lawrence Rauchwerger	Texas A and M University
Erven Rohou	INRIA
Mitsuhisa Sato	RIKEN
Albert Sidelnik	NVIDIA
Xinmin Tian	Intel
Mateo Valero	Barcelona Supercomputing Center / UPC
Jeffrey S. Vetter	ORNL
Pen-Chung Yew	University of Minnesota

2017 Workshop Page