REV-A Workshop

Re-Emergence of Vector Architectures

To be held in conjunction with the IEEE Cluster 2017

REV-A Submission

The commoditization of high performance computing to a broader range of applications coupled with the reduction in performance improvement from traditional scaling technologies has led to a broad interest in a number of new compute acceleration technologies from GPGPUs to CGRAs and FPGAs. Meanwhile, SIMD widths have been widening to try to keep up with computational demand and general purpose architectures have started incorporating features from the vector architectures that used to dominate high performance computing. From IBM's Vector Media eXtension (VMX) to NEC's SX architecture to Intel's Advanced Vector eXtension (AVX) to ARM's recently announced Scalable Vector Extension (SVE) -- all of the major general purpose architectures seem to have embraced a return to vector based functionality.

Supporting these hardware developments there are a number of features being proposed for incorporation into modern programming models and languages in order to support the vector additions as well as restructuring memory access in order to feed the computational pipelines. Meanwhile application developers have been hard at work trying to refactor code to take advantage of wider vector units and more complicated memory hierarchies. Tools and techniques for developing for these new vector architectures are still evolving, particularly on emerging languages and runtimes.

Location: Waianae Room - Sheraton Waikiki

Dr. Hiroshi Nakashima

Finding Regularity in Problems with Irregularity


Vectorized computation especially on scalar processors with wide SIMD mechanism requires regularity. For example, though such a processor has gather/scatter capability for irregular memory accesses, they are much less efficient than ordinary consecutive accesses mainly due to, in speaker's opinion, the line-oriented configuration of caches. Unfortunately, real HPC programs often have such irregular accesses to a vector multiplied to a sparse matrix in CRS format, to a linear list to represent a set of objects, and so on, and thus fail to exploit SIMD-vector mechanism efficiently. However, HPC problems (not programs) with sparse matrices, dynamically configured sets, etc. may have some degree of regularity because such objects can be represented in some form with regularity. In this talk, a few examples in which regularity is found and exploited are presented to discuss the importance of programming effort and of the way to reduce the amount of efforts made by programmers.


Dr. Hiroshi Nakashima is working in Academic Center for Computing and Media Studies, Kyoto University as a professor who is responsible for the design and operation of supercomputers in the Center and for collaborative HPC researches with the supercomputers. Prior to join in the Center, he had been a professor of Toyohashi University of Technology, an associate professor of Kyoto University, and a researcher in Mitsubishi Electric Corporation. He received his B.E., M.E. and PhD from Kyoto University in 1979, 1981 and 1991, respectively.

The REV-A 2017 workshop will be a full-day meeting to be held at the IEEE Cluster 2017, in Honolulu, Hawaii, focusing on all aspects of vector architectures, programming models, programming frameworks, and applications. Topics of interest, of both theoretical and practical significance, include but are not limited to the following topics:

The REV-A workshop proceedings will be published along with the IEEE Cluster Digital Library. Submitted manuscripts should follow the IEEE Xplore format for publication: not exceed 10 single-spaced double-column pages using 10-point size font on 8.5x11 inch pages, including figures, tables, and references. Manuscripts must be submitted electronically in PDF format. Submissions will be judged on correctness, originality, technical strength, significance, quality of presentation, and interest and relevance to the workshop attendees. Submitted papers may not have appeared in or be under consideration for another workshop, conference, or journal. Accepted papers will have a page limit of 8 pages, and authors can purchase an additional 2 pages, for a total of 10 pages maximum.

Deadlines are Anywhere on Earth (AoE)

      Full Papers due:   June 25, 2017
      Paper Acceptance Notification:   July 17, 2017
      Camera-ready deadline:   July 30, 2017
      REV-A Workshop:   September 05, 2017
      Luiz DeRose   Cray Inc.
      Eric Van Hensbergen       ARM Research
      David Abramson   University of Queensland
      Bronis R. de Supinski   Lawrence Livermore National Laboratory
      Mootaz Elnozahy   KAUST
      Roger Espasa   SemiDynamics
      Michael Garland   NVIDIA
      Ian Karlin   Lawrence Livermore National Laboratory
      David Lilja   University of Minnesota
      Sally McKee   Chalmers University of Technology
      Sanyam Mehta   Cray Inc.
      Hiroshi Nakashima   Kyoto University
      Lawrence Rauchwerger   Texas A&M University
      Mitsuhisa Sato   Riken
      Sunil Shrestha   Cray Inc.
      Xinmin Tian   Intel
      Mateo Valero   Barcelona Supercomputing Center / UPC
      Jeffrey Vetter   Oak Ridge National Laboratory
      Felix Wolf   TU Darmstadt
      Pen-Chung Yew   University of Minnesota